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About this product
- PublisherSpringer-Verlag New York Inc.
- Date of Publication12/02/2010
- GenreElectronics Engineering & Communications Engineering
- Series TitleIFIP Advances in Information and Communication Technology
- Series Part/Volume Numberv. 240
- Place of PublicationNew York, NY
- Country of PublicationUnited States
- ImprintSpringer-Verlag New York Inc.
- Content Note176 black & white illustrations, 55 black & white tables, biography
- Weight545 g
- Width156 mm
- Height234 mm
- Spine18 mm
- Edited byAdam Osseiran,Hans-Joerg Pfleiderer,Ricardo Reis
- Format DetailsTrade paperback (US)
- Edition Statement1st ed. Softcover of orig. ed. 2007
- Table Of ContentsMolecular Electronics - Devices and Circuits Technology.- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.- Defragmentation Algorithms for Partially Reconfigurable Hardware.- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.- Issues in Model Reduction of Power Grids.- A Traffic Injection Methodology with Support for System-Level Synchronization.- Pareto Points in SRAM Design Using the Sleepy Stack Approach.- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.- A Novel MicroPhotonic Structure for Optical Header Recognition.- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.- Exact BDD Minimization for Path-Related Objective Functions.- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.
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