CURRENTLY SOLD OUT
Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering by Ben U Seng Pan, Rui Paulo da Silva Martins, Jose E. Franca (Paperback, 2010)
Best-selling in Adult Learning & University
Save on Adult Learning & University
- £9.10Trending at £10.98
- £26.45Trending at £27.79
- £11.12Trending at £13.99
- £7.44Trending at £8.98
- £10.89Trending at £12.29
- £18.09Trending at £19.20
- £15.21Trending at £18.61
About this product
- Author(s)Ben U Seng Pan,Jose E. Franca,Rui Paulo da Silva Martins
- PublisherSpringer-Verlag New York Inc.
- Date of Publication12/02/2010
- GenreElectronics Engineering & Communications Engineering
- Series TitleThe Springer International Series in Engineering and Computer Science
- Series Part/Volume Number867
- Place of PublicationNew York, NY
- Country of PublicationUnited States
- ImprintSpringer-Verlag New York Inc.
- Content Notebiography
- Weight370 g
- Width156 mm
- Height234 mm
- Spine13 mm
- Format DetailsTrade paperback (US)
- Edition Statement1st ed. Softcover of orig. ed. 2006
- Table Of ContentsDedication. Preface. Acknowledgment. List of Abbreviations. List of Figures. List of Tables. 1. Introduction. 1. High-Frequency Integrated Analog Filtering. 2. Multirate Switched-Capacitor Circuit Techniques. 3. Sampled-Data Interpolation Techniques. 4. Research Goals and Design Challenges. 2. Improved Multirate Polyphase-Based Interpolation Structures. 1. Introduction. 2. Conventional and Improved Analog Interpolation. 3. Polyphase Structures for Optimum-class Improved Analog Interpolation. 4. Multirate ADB Polyphase Structures. 5. Low-Sensitivity Multirate IIR Structures. 6. Summary. 3. Practical Multirate SC Circuit Design Considerations. 1.Introduction. 2. Power Consumption Analysis. 3. Capacitor-Ratio Sensitivity Analysis. 4. Finite Gain & Bandwidth Effects. 5. Input-Referred Offset Effects. 6. Phase Timing-Mismatch Effects. 7. Noise Analysis. 8. Summary. 4. Gain- and Offset-Compensation for Multirate SC Circuits. 1. Introduction. 2. Autozeroing and Correlated-Double Sampling Techniques. 3. AZ and CDS SC Delay Blocks with Mismatch-Free Property. 4. AZ and CDS SC Accumulators. 5. Design Examples. 6. Speed and Power Considerations. 7. Summary. 5. Design of a 108 MHz Multistage SC Video Interpolating Filter. 1. Introduction. 2. Optimum Architecture Design. 3. Circuit Design. 4. Circuit Layout. 5. Simulation Results. 6. Summary. 6. Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter. 1. Introduction. 2. Prototype System-Level Design. 3. Prototype Circuit-Level Design. 4. Layout Considerations. 5. Simulation Results. 6. Summary. 7. Experimental Results. 1. Introduction. 2. PCB Design. 3. Measurement Setup and Results. 4. Summary. 8. Conclusions. Appendix 1.Timing-Mismatch Errors with Nonuniformly Holding Effects. 1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH). 2. Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH). 3. Closed Form SFDR Expression for IN-CON(SH) systems. 4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH). Appendix 2. Noise Analysis For SC ADB Delay Line and Polyphase Subfilters. 1. Output Noise of ADB Delay Line. 2. Output Noise of Polyphase Subfilters. Appendix 3. Gain, Phase and Offset Errors for GOC MF SC Delay Circuit i and j. 1. GOC MF SC Delay Circuit i. 2. GOC MF SC Delay Circuit j.
This item doesn't belong on this page.
Thanks, we'll look into this.