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About this product
- DescriptionUsing Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design practices and methodologies.
- Author BiographyAbout the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi's involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.
- Author(s)Zainalabedin Navabi
- PublisherSpringer-Verlag New York Inc.
- Date of Publication18/12/2010
- GenreElectronics Engineering & Communications Engineering
- Place of PublicationNew York, NY
- Country of PublicationUnited States
- ImprintSpringer-Verlag New York Inc.
- Content Notebiography
- Weight1011 g
- Width178 mm
- Height254 mm
- Spine25 mm
- Format DetailsLaminated cover
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