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About this product
- Author(s)Ahmed Helmy,Mohammed Ismail
- PublisherSpringer-Verlag New York Inc.
- Date of Publication07/04/2008
- GenreElectronics Engineering & Communications Engineering
- Series TitleAnalog Circuits and Signal Processing
- Place of PublicationNew York, NY
- Country of PublicationUnited States
- ImprintSpringer-Verlag New York Inc.
- Content Notebiography
- Weight371 g
- Width156 mm
- Height234 mm
- Spine9 mm
- Format DetailsLaminated cover
- Table Of ContentsAbstract. Dedication. Acknowledgements. Vita. List of Tables. List of Figures. Chapter 1. Introduction. Motivation and Research Objectives. Contributions Thesis Organization. Chapter 2. Analysis of Substrate Noise Coupling. Process Regions. Process cross sections. Connection of devices to the substrate. Devices directly connected to the substrate network. Devices indirectly connected to the substrate network. Noise coupling mechanism. Substrate Noise Injection Mechanisms. Substrate Noise Reception Mechanisms. Substrate Noise Transmission Mechanisms. Substrate doping profile tradeoffs. Substrate Model extraction in the IC design flow. Doping Profile Considerations. Substrate model extraction kernels. Finite Difference method. Boundary Element method. Comparison between the two Techniques. Approximations in the Model Extraction Algorithm. Conclusion. Chapter 3. Experimental Data to calibrate the design flow. Introduction. The test chip. Baseline Isolation. Data analysis. Effect of p-guard ring on isolation. Data analysis. Effect of n-guard ring on isolation. Data analysis. Effect of deep n-well on isolation. Data analysis. Effect of deep trench on isolation. Data analysis. De-embedding. Conclusion. Chapter 4. Design Guide for Substrate Noise Isolation for RF Applications Introduction. Isolation in Low resistivity substrate. Isolation vs. Frequency for different isolation structures. Effect of back plane connection on the noise isolation in high resistivity substrates. Substrate Contacts: Front side or Backside? Both. P+ Guard Ring Isolation. Guard Ring Isolation vs. D. Guard Ring grounding scheme. Guard Ring Isolation vs. d. Guard Ring Isolation vs. 'w'. P+ and N+ Guard Rings Isolation. Floor planning techniques to minimize coupling. Circuit techniques to minimize coupling. Active guard rings. Conclusion. Chapter 5. On Chip Inductor Design Flow. Introduction. Integrated Inductors. Inductor Design Flow. Analytical exploration of the design space. Inductor Model and Substrate Parasitics. Calibrating the field solver. Model fit. DFM effects. Impact of bumps. Impact of temperature variation. Impact of process variation. Impact of metal fill. Conclusion. Chapter 6. Case studies for the impact and remedy of substrate noise coupling. Introduction. System Level Case study. Background. Design Data. Block Level Case study. Design details. Device Level Case study. Conclusion. Chapter 7. Conclusion and Future work. Appendix A Scattering Parameters. Appendix B Measurements Setup. Bibliography.
- Author BiographyMohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series
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