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Loop Tiling for Parallelism by Jingling Xue: New
US $188.13
Approximately£147.69
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Located in: Sparks, Nevada, United States
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eBay item number:364246935344
Item specifics
- Condition
- Book Title
- Loop Tiling for Parallelism
- Publication Date
- 2000-08-31
- Pages
- 256
- ISBN
- 9780792379331
- Publication Year
- 2000
- Series
- The Springer International Series in Engineering and Computer Science Ser.
- Type
- Textbook
- Format
- Hardcover
- Language
- English
- Publication Name
- Loop Tiling for Parallelism
- Item Length
- 9.3in
- Publisher
- Springer
- Item Width
- 6.1in
- Item Weight
- 44.4 Oz
- Number of Pages
- Xix, 256 Pages
About this product
Product Information
Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.
Product Identifiers
Publisher
Springer
ISBN-10
0792379330
ISBN-13
9780792379331
eBay Product ID (ePID)
1792944
Product Key Features
Publication Name
Loop Tiling for Parallelism
Format
Hardcover
Language
English
Publication Year
2000
Series
The Springer International Series in Engineering and Computer Science Ser.
Type
Textbook
Number of Pages
Xix, 256 Pages
Dimensions
Item Length
9.3in
Item Width
6.1in
Item Weight
44.4 Oz
Additional Product Features
Series Volume Number
575
Number of Volumes
1 Vol.
Lc Classification Number
Tk7895.M5
Table of Content
I Mathematic Background and Loop Transformation.- 1. Mathematical Background.- 2. Nonsingular Transformations And Permutabidlity.- II Tiling as a Loop Transformation.- 3. Rectangular Tiling.- 4. Parallelepiped Tiling.- III Tiling for Distributed-Memory Machines.- 5. Spmd Code Generation.- 6. Communication-Minimal Tiling.- 7. Time-Minimal Tiling.
Copyright Date
2000
Topic
Systems Architecture / General, Systems Architecture / Distributed Systems & Computing, Computer Science
Lccn
00-057639
Dewey Decimal
004/.35
Intended Audience
Scholarly & Professional
Dewey Edition
21
Illustrated
Yes
Genre
Computers
Item description from the seller
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Alibris, Inc.
Rob Lambert
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